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Power: Front & Center of the Silicon Design Process

April 6, 2022

Power is one of the most critical design metrics today, but it still is an afterthought in far too many…

By Mathilde Karsenti
2 MIN READ
image of source code running through Catapult provides the same latency for the AES core

Conversion from Vivado High-Level Synthesis (HLS) to Catapult HLS

March 5, 2021

In this blog post, we explore the key points which are required to convert an algorithm developed for Vivado HLS…

By Mathilde Karsenti
4 MIN READ
SemiWiki: Mentor Masterclass on ML SoC Design

SemiWiki: Mentor Masterclass on ML SoC Design

March 24, 2020

Excerpt from article: “Mentor Masterclass on ML SoC Design” I was scheduled to attend the Siemens EDA tutorial at DVCon…

By nileshthiagarajan
< 1 MIN READ
Master the design and verification of next gen transport: Part Two – high-level synthesis

Master the design and verification of next gen transport: Part Two – high-level synthesis

October 2, 2019

Excerpt from article: “Master the design and verification of next gen transport: Part Two – high-level synthesis” Part one of…

By nileshthiagarajan
< 1 MIN READ
Synthesizing Hardware From Software

Synthesizing Hardware From Software

August 22, 2019

Excerpt from article: “Synthesizing Hardware From Software” In the past, many co-processor solutions have been dogged by communications costs. “There…

By nileshthiagarajan
< 1 MIN READ
Building an ecosystem around HLS for AI and ML designs

Building an ecosystem around HLS for AI and ML designs

June 27, 2019

Excerpt from article: “Building an ecosystem around HLS for AI and ML designs“ HLS has been gaining traction in AI because,…

By nileshthiagarajan
< 1 MIN READ