From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

As we gear up for the 62nd Design Automation Conference (DAC) in San Francisco, one of the most anticipated events…

Questa One DFT Verification

DFT Verification: Tackling the evolving challenges

Technological advancement continues as a blistering pace, and the demand for highly reliable systems is paramount across various industries. Safety…

User2User

Closing the Gap in Software Skills for Verification Engineers

I’m excited to announce next month’s U2U (User-to-User) meeting, followed by a crucial technical training session that no hardware verification…

DVCon 2025: A must for hardware design and verification engineers

I’ve attended every DVCon US conference since its inception, over 30 years ago. I’ve also given keynotes at DVCon India….

Siemens at DVCon 2025: Don’t Miss the Luncheon and More!

The latest trends in verification are in—and they’re more than just surprising. They’re alarming. Join Siemens EDA at DVCon 2025 for an exclusive luncheon…

Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard

Accellera Systems Initiative approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard.  This milestone marks a significant advancement in…

Breaking the Bottleneck: A Smarter Approach to Semiconductor Verification

The semiconductor industry is facing a new reality: traditional verification methods can no longer keep pace with the rapid evolution…

Accellera Sessions at DVCon U.S. 2025

As one of Accellera’s Global Sponsors, Siemens EDA is happy to help shape the Accellera sessions at DVCon U.S and…

Unlocking the Future of High Bandwidth Memory with Siemens and Rambus

In a recent webinar, Siemens partnered with Rambus to delve into the transformative world of High Bandwidth Memory (HBM), focusing…